1. NAND Flash Interface

Interface between cpu and chips. Why? I was wondering about best filesystem for my external SSD, because obviously write-cached external device is bad. I always just unplug my drive without unmounting and ejecting, so I’m always afraid about data corruption. So, i was searching about flash-friendly file systems, and I found JIFFS2 or UBIFS?. JIFFS was familliar, I have seen it from many embedded board projects. It was raw NAND chip friendly. We need FAL? (Flash Abstract Layer) when we use flash chips. But we dont care about these in ssds. Why? Because SSD Controllers embedded in ssd itself manages this abstraction and also controls wearing, also caching in local DRAM. So, we dont need to care about these things when we use SSD. But in embedded board that normally doesnt have seperate controller rather than just attaching NAND chips directly to CPU. Like NOR chip I used several times, NAND is also connected directly. I used QSPI when connecting NOR chip, but SPI was not sufficient for high-speed high data-rate NAND chips. We need parallel communicaion. Even though I have seen a lot of NAND projects, I never saw this part of firmware controlling and parsing NAND signals. I’ve seen NAND controller firmware that does block-level jobs, but never this interfacing things. So I searched a bit about NAND interface, and I found that there arent many standards in this part. There was ONFI (Open NAND Flash Interface) that defines standard interface for NAND chips, but not many major chips supported, maybe. I saw some documentations like Micron’s, and well, that was complex. I dont know yet about hardware timing and things like that, not about that low-level of things. Well but I was interested about that things. Also I learned about Eth PHY and interfaces like MII, GMII… It defines signal level interface and again I am not familiar with these things. And, this was all thing I searched about.